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Datasheet File OCR Text:

19-5004; Rev 0; 11/09
TION KIT EVALUA BLE AVAILA
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
General Description Features
S 2.7V to 5.5V Single Supply Voltage S 725mW Speaker Output (VPVDD = 3.7V, ZSPK = 8I + 68H) S 40mW/Channel Headphone Output (RHP = 16I) S Low-Emission Class D Amplifier S Efficient Class H Headphone Amplifier S Ground-Referenced Headphone Outputs S Two Stereo Single-Ended/Mono Differential Inputs S Integrated Distortion Limiter (Speaker Outputs) S Integrated DPST Analog Switch S No Clicks and Pops S TDMA Noise Free S 2mm x 2mm, 25-Bump 0.4mm Pitch WLP Package
MAX97000
The MAX97000 audio subsystem combines a mono speaker amplifier with a stereo headphone amplifier and an analog DPST switch. The headphone and speaker amplifiers have independent volume control and on/off control. The four inputs are configurable as two differential inputs or four single-ended inputs. The entire subsystem is designed for maximum efficiency. The high-efficiency 725mW Class D speaker amplifier operates directly from the battery and consumes no more than 1FA in shutdown mode. The Class H headphone amplifier utilizes a dual-mode charge pump to maximize efficiency while outputting a ground-referenced signal that does not require output coupling capacitors. The speaker amplifier incorporates a distortion limiter to automatically reduce the volume level when excessive clipping occurs. This allows high gain for low-level signals without compromising the quality of large signals. All control is performed using the 2-wire, I2C interface. The MAX97000 operates in the extended -40NC to +85NC temperature range, and is available in the 2mm x 2mm, 25-bump WLP package (0.4mm pitch).
Ordering Information
PART MAX97000EWA+ TEMP RANGE -40NC to +85NC PIN-PACKAGE 25 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Applications
Cell Phones Portable Multimedia Players
Simplified Block Diagram
BATTERY 2.7V TO 5.5V I2C
POWER SUPPLY
CONTROL
MAX97000
STEREO/ MONO INPUT
LIMITER
VOLUME
CLASS D AMPLIFIER
STEREO/ MONO INPUT
VOLUME
CLASS H AMPLIFIER CHARGE PUMP
SWITCH
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional Diagram/Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Digital I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Internal Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Class D Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ultra-Low EMI Filterless Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DirectDrive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Class H Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2 C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
TABLE OF CONTENTS (CONTINUED)
Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Charge-Pump Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Early STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
MAX97000
3
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
Functional Diagram/Typical Application Circuit
2.5V TO 5.5V
2.7V TO 5.5V
10F
1F VDD B1
1F LDOIN B2 LDO PVDD C1
1F
10F
MUX
0.47F OPTIONAL
PGAINA -6dB TO +18dB
BIAS
C5 BIAS 1F
INA1 E4
INADIFF
LPMODE
HPLVOL: -64dB TO +6dB PGAINA -6dB TO +18dB
HPVDD CLASS H 0/3dB HPLEN HPVSS HPVDD
HPRVOL: -64dB TO +6dB
B5 HPL
0.47F OPTIONAL
INA2 E5
+
HPLMIX
MIX
0.47F OPTIONAL
PGAINB -6dB TO +18dB
CLASS H 0/3dB HPREN HPVSS PVDD
A5 HPR
INB1 D4
INBDIFF
HPRMIX
SPKVOL: -30dB TO +20dB
MIX
E1 OUTP CLASS D +12dB SPKEN PGND THD LIMITER D1 OUTN
0.47F OPTIONAL
PGAINB -6dB TO +18dB
SPKMIX
INB2 D5
+
ANALOG SWITCHES
MIX
THDCLP E2 NC1 E3 NC2
COM1 D2 COM2 D3 VDD SDA B3 SCL B4 SHDN C4 I2C INTERFACE/ SHUTDOWN C3 GND VDD SWEN
MAX97000
C2 PGND A1 C1P
CHARGE PUMP A2 C1N 1F 1F A3 HPVDD A4 HPVSS 1F
4
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
ABSOLUTE MAXIMUM RATINGS
(Voltages with respect to GND.) VDD, HPVDD ........................................................-0.3V to +2.2V PVDD, LDOIN .......................................................-0.3V to +6.0V PGND ...................................................................-0.1V to +0.1V HPVSS .................................................................-2.2V to + 0.3V C1N ..................................... (HPVSS - 0.3V) to (HPVDD + 0.3V) C1P ..........................................................- 0.3V to (VDD + 0.3V) HPL, HPR ............................. (HPVSS - 0.3V) to (HPVDD +0.3V) INA1, INA2, INB1, INB2, BIAS .............................-0.3V to +6.0V SDA, SCL, SHDN .................................................-0.3V to +6.0V COM1, COM2, NC1, NC2, OUTP, OUTN ......................................-0.3V to (PVDD + 0.3V) Continuous Current In/Out of PVDD, PGND, OUT_ ...... Q800mA Continuous Current In/Out of HPR, HPL, VDD, LDOIN .............................................................. Q140mA Continuous Current In/Out of COM1, COM2, NC1, NC2 ...................................................... Q150mA Continuous Input Current (all other pins) ........................ Q20mA Duration of OUT_ Short Circuit to GND or PVDD .................................................................Continuous Duration of Short Circuit Between OUTP and OUTN .............................................................Continuous Duration of HP_ Short Circuit to GND or VDD ..........Continuous Continuous Power Dissipation (TA = +70NC) Multilayer Board 25 WLP (derate 19.2mW/NC above +70NC) ................850mW Junction Temperature .....................................................+150NC Operating Temperature Range .......................... -40NC to +85NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+260NC
MAX97000
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Speaker Amplifier SupplyVoltage Range LDO Input Supply-Voltage Range SYMBOL VPVDD VLDOIN CONDITIONS Guaranteed by PSRR test Guaranteed by PSRR test Low-power mode, TA = +25NC, LPMODE = 0x01 HP mode, TA = +25NC, stereo SE input on INA, INB disabled Quiescent Supply Current SPK mode, TA = +25NC mono differential input on INB, INA disabled SPK + HP mode, TA = +25NC stereo SE input on INA, INB disabled ISHDN TA = +25NC, internal gain, software ILDOIN IPVDD ILDOIN IPVDD ILDOIN IPVDD ILDOIN IPVDD IPVDD ILDOIN MIN 2.7 2.5 1.45 0.4 1.45 0.79 0.42 1.38 1.45 1.8 90 60 TYP MAX 5.5 5.5 2 0.7 2 1.2 0.75 2.2 2 2.7 175 110 1 8 41.2 16 5.5 19 20.6 7.2 20 27 9.5 21 kI 5 kI ms FA mA UNITS V V
Shutdown Current
TA = +25NC, internal gain, IPVDD + ILDOIN, hardware Time from power-on to full operation including soft-start TA = +25NC, internal gain Gain = -6dB, -3dB Gain = 0dB to +9dB Gain = +18dB
Turn-On Time
tON
Input Resistance Feedback Resistance
RIN RF
TA = +25NC, external gain
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
ELECTRICAL CHARACTERISTICS (continued)
(VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL= SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL Preamp = 0dB Maximum Input Signal Swing Preamp = +18dB Preamp = external gain Common-Mode Rejection Ratio Input DC Voltage Bias Voltage SPEAKER AMPLIFIER TA = +25NC, SPKM = 1 Output Offset Voltage VOS TA = +25NC, SPKVOL = 0dB, SPKMIX = 0x01, IN_DIFF = 0V Peak voltage, TA = +25NC, A-weighted, 32 samples per second, volume at mute (Note 2) Into shutdown Out of shutdown VPVDD = 2.7V to 5.5V f = 217Hz, VRIPPLR = 200mVP-P PSRR TA = +25NC (Note 2) f = 1kHz, VRIPPLR = 200mVP-P f = 20kHz, VRIPPLR = 200mVP-P Output Power THD+N P 1%, f = 1kHz, ZSPK = 8I + 68FH (Note 3) THD+N VPVDD = 4.2V VPVDD = 3.7V VPVDD = 3.3V 50 Q0.5 Q1.5 -70 dBV -70 75 65 65 59 930 725 562 0.05 93 93 250 Q20 11.5 E POUT = 725mW, f = 1kHz, ZSPK = 8I + 68FH A-weighted, (SPKMIX = 0x01), IN_DIFF = 1, SPKVOL = 0dB 12 1.5 87 50 12.5 kHz kHz dB A % FVRMS 0.6 % mW dB Q4 mV VBIAS CMRR f = 1kHz (differential input mode) IN__ inputs Gain = 0dB Gain = +18dB 1.125 1.13 CONDITIONS MIN TYP 2.3 0.29 2.3 x RIN,EX/ RF 55 32 1.2 1.2 1.275 1.27 VP-P MAX UNITS
dB V V
Click-and-Pop Level
KCP
Power-Supply Rejection Ratio
Total Harmonic Distortion + Noise Signal-to-Noise Ratio Oscillator Frequency Spread-Spectrum Bandwidth Gain Current Limit Efficiency Output Noise
f = 1kHz, POUT = 360mW, TA = +25NC, ZSPK = 8I + 68FH A-weighted, SPKMIX IN_DIFF = 0 = 0x03, referenced to (single-ended) 725mW IN_DIFF = 1 (differential)
SNR fOSC
dB
6
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL= SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER CHARGE PUMP VHPL = VHPR = 0V Charge-Pump Frequency VHPL = VHPR = 0.2V VHPL = VHPR = 0.5V Positive Output Voltage Negative Output Voltage VHPVDD VHPVSS VTH1 VTH2 VHPL, VHPR > VTH VHPL, VHPR < VTH VHPL, VHPR > VTH VHPL, VHPR < VTH Output voltage at which the charge pump switches between fast and slow clock Output voltage at which the charge pump switches modes, VOUT rising or falling Time it takes for the charge pump to transition from invert to split mode Time it takes for the charge pump to transition from split to invert mode TA = +25NC volume at mute Output Offset Voltage VOS TA = +25NC, HP_VOL = 0dB, HP_MIX = 0x1, IN_DIFF = 0 Peak voltage, TA = +25NC, A-weighted, 32 Into shutdown samples per second, volume at mute Out of shutdown (Note 2) VLDOIN = 2.5V to 5.5V f = 217Hz, VRIPPLE = 200mVP-P PSRR TA = +25NC (Note 2) f = 1kHz, VRIPPLE = 200mVP-P f = 20kHz, VRIPPLE = 200mVP-P RHP = 16I Output Power POUT THD+N = 1%, f = 1kHz RHP = 32I RHP = 32I, LPMODE = 1, LP gain = 3dB 70 0.1 0.40 80 83 665 500 1.8 0.9 -1.8 -0.9 0.16 0.46 32 20 0.21 V 0.52 ms Fs V V 85 kHz SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX97000
Headphone Output Voltage Threshold
Mode Transition Timeouts
HEADPHONE AMPLIFIERS Q0.15 Q0.5 -74 dBV -74 85 84 80 62 40 23 34 mW dB Q0.6 mV
Click-and-Pop Level
KCP
Power-Supply Rejection Ratio
Channel-to-Channel Gain Tracking
TA = +25NC, HPL to HPR, volume at maximum, HPLMIX = 0x01, HPRMIX = 0x02, IN_DIFF = 0
Q0.3
Q2.5
%
7
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
ELECTRICAL CHARACTERISTICS (continued)
(VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL= SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Total Harmonic Distortion + Noise Signal-to-Noise Ratio Slew Rate Capacitive Drive Crosstalk ANALOG SWITCH On-Resistance RON INC_ = 20mA, VCOM_ = 0V and PVDD, SWEN = 1 VDIFCOM_ = 2VP-P, VCMCOM_= PVDD/2, f = 1kHz, SWEN = 1, ZSPK = 8I + 68FH TA = +25NC TA = TMIN to TMAX 10I in series with each switch No series resistors 0.05 % 0.3 1.6 4 I 5.2 SYMBOL THD+N SNR SR CL HPL to HPR, HPR to HPL, f = 20Hz to 20kHz POUT = 10mW, f = 1kHz CONDITIONS RHP = 32I RHP = 16I MIN TYP 0.02 0.03 100 0.35 200 65 0.1 MAX UNITS % dB V/Fs pF dB
A-weighted, RHP = 16I, HPLMIX = 0x01, HPRMIX = 0x02, IN_DIFF = 0
Total Harmonic Distortion + Noise
Off-Isolation PREAMPLIFIER
SWEN = 0, COM1 and COM2 to GND = 50I, f = 10kHz, referred to signal applied to NC1 and NC2 PGAIN_ = 000 PGAIN_ = 001 PGAIN_ = 010 -6.5 -3.5 -0.5 2.5 5.5 8.5 17.5 5.5 -68 19 -31 Speaker Headphone
105
dB
-6 -3 0 3 6 9 18 6 -64 20 -30 109 101 100
-5.5 -2.5 0.5 3.5 6.5 9.5 18.5 6.5 -60 21 -29 dB ms dB dB
Gain
PGAIN_ = 011 PGAIN_ = 100 PGAIN_ = 101 PGAIN_ = 110
VOLUME CONTROL HP_VOL = 0x1F Volume Level HP_VOL = 0x00 SPKVOL = 0x3F SPKVOL = 0x00 Mute Attenuation Zero-Crossing Detection Timeout LIMITER Attack Time Release Time Constant 8 THDT1 = 0 THDT1 = 1 1 1.4 2.8 ms s f = 1kHz
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
DIGITAL I/O CHARACTERISTICS
(VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN 1.3 0.5 200 10 TA = +25NC VLDOIN = 0, TA = +25NC ISINK = 3mA Q1.0 Q1.0 0.4 TYP MAX UNITS V V mV pF FA
MAX97000
DIGITAL INPUTS (SDA, SCL, SHDN) Input Voltage High VIH Input Voltage Low Input Hysteresis Input Capacitance Input Leakage Current VIL VHYS CIN IIN
DIGITAL OUTPUTS (SDA Open Drain) Output Low Voltage VOL V
I2C TIMING CHARACTERISTICS
(VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Serial-Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition SCL Pulse-Width Low SCL Pulse-Width High Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time SDA and SCL Receiving Fall Time SDA Transmitting Fall Time Setup Time for STOP Condition Bus Capacitance Pulse Width of Suppressed Spike Note Note Note Note 1: 2: 3: 4: SYMBOL fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tR tF tF tSU,STO CB tSP 0 (Note 4) (Note 4) (Note 4) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 400 50 300 300 300 900 TYP MAX 400 UNITS kHz Fs Fs Fs Fs Fs ns ns ns ns ns Fs pF ns
100% production tested at TA = +25NC. Specifications overtemperature limits are guaranteed by design. Amplifier inputs are AC-coupled to GND. Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. CB is in pF.
9
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
SDA tSU,DAT tHD,DAT tHIGH tSU,STA tBUF tHD,STA tSP tSU,STO
tLOW SCL tHD,STA tR START CONDITION
tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 1. I2C Interface Timing Diagram
Typical Operating Characteristics
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
GENERAL
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX97000 toc01
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
4.0 SHUTDOWN CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 HARDWARE INPUTS AC-COUPLED TO GND SOFTWARE
MAX97000 toc02
3.0 2.5 SUPPLY CURRENT (mA) 2.0 1.5 1.0 0.5 0 2.5 3.0 3.5 4.0 4.5 5.0 SPEAKER ONLY INPUTS AC-COUPLED TO GND INA CONNECTED TO OUTPUT
4.5
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
10
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
MAX97000
SPEAKER AMPLIFIER
THD+N vs. FREQUENCY
MAX97000 toc03
THD+N vs. FREQUENCY
MAX97000 toc04
THD+N vs. FREQUENCY
VPVDD = 3.7V ZSPRK = 8I + 68F 1
MAX97000 toc05
10 VPVDD = 3.7V ZSPRK = 8I + 68F 1 THD+N (%)
10 VPVDD = 3.7V ZSPRK = 4I + 33F 1 THD+N (%) POUT = 1000mW
10
0.1
POUT = 500mW
0.1
THD+N (%)
0.1 SSM 0.01 FFM
0.01
POUT = 200mW
0.01
POUT = 200mW
0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100
0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100
0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100
THD+N vs. OUTPUT POWER
MAX97000 toc06
THD+N vs. OUTPUT POWER
MAX97000 toc07
THD+N vs. OUTPUT POWER
VPVDD = 4.2V ZSPRK = 8I + 68F
MAX97000 toc08
100 10 THD+N (%) 1 0.1 0.01 0.001 0 0.5 1.0 1.5 2.0 VPVDD = 5.0V ZSPRK = 8I + 68F
100 10 THD+N (%) 1 0.1 0.01 fIN = 100Hz 0.001 VPVDD = 5.0V ZSPRK = 4I + 33F
100 10 THD+N (%) 1 0.1 0.01 0.001
fIN = 6kHz fIN = 1kHz
fIN = 6kHz fIN = 1kHz
fIN = 6kHz fIN = 1kHz
fIN = 100Hz
fIN = 100Hz
2.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
POUT (mW)
POUT (mW)
POUT (mW)
THD+N vs. OUTPUT POWER
MAX97000 toc09
THD+N vs. OUTPUT POWER
MAX97000 toc10
THD+N vs. OUTPUT POWER
VPVDD = 3.7V ZSPRK = 4I + 33F fIN = 6kHz THD+N (%) 1 0.1 0.01 0.001 fIN = 1kHz
MAX97000 toc11
100 10 THD+N (%) 1 0.1 0.01 fIN = 100Hz 0.001 0 0.5 1.0 1.5 POUT (mW) 2.0 2.5 fIN = 1kHz VPVDD = 4.2V ZSPRK = 4I + 33F fIN = 6kHz
100 10 THD+N (%) 1 0.1 0.01 0.001 fIN = 1kHz VPVDD = 3.7V ZSPRK = 8I + 68F fIN = 6kHz
100 10
fIN = 100Hz
fIN = 100Hz 0 0.5 1.0 1.5 2.0 2.5
3.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
POUT (mW)
POUT (mW)
11
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
EFFICIENCY vs. OUTPUT POWER
MAX97000 toc12
EFFICIENCY vs. OUTPUT POWER
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 3.0 0 0.2 0.4 0.6 0.8 ZSPRK = 4I + 33F ZSPRK = 8I + 68F
MAX97000 toc13
OUTPUT POWER vs. SUPPLY VOLTAGE
3.5 OUTPUT POWER (W) 3.0 2.5 2.0 1.5 1.0 0.5 0 1.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 THD+N = 1% THD+N = 10% fIN = 1kHz ZSPRK = 4I + 33F
MAX97000 toc14
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0
ZSPRK = 8I + 68F ZSPRK = 4I + 33F
100
4.0
VPVDD = 5.0V fIN = 1kHz 0.5 1.0 1.5 POUT (W) 2.0 2.5
VPVDD = 3.7V fIN = 1kHz 1.0 1.2 1.4
POUT (W)
SUPPLY VOLTAGE (V)
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX97000 toc15
OUTPUT POWER vs. LOAD RESISTANCE
MAX97000 toc16
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
VPVDD = 3.7V VRIPPLE = 200mVP-P INPUTS AC-COUPLED GND
MAX97000 toc17
2.0 1.8 1.6 OUTPUT POWER (W) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 3.0 3.5 4.0 4.5 5.0 THD+N = 1% fIN = 1kHz ZSPRK = 8I + 68F THD+N = 10%
2.0 1.8 1.6 OUTPUT POWER (W) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 THD+N = 1% VPVDD = 3.7V fIN = 1kHz ZSPRK = LOAD + 68F THD+N = 10%
0 -20 -40 -60 -80 -100
PSRR (dB)
5.5
1
10
100
1000
0.01
0.1
1 FREQUENCY (kHz)
10
100
SUPPLY VOLTAGE (V)
LOAD RESISTANCE (I)
POWER-SUPPLY REJECTION RATIO vs. SUPPLY VOLTAGE
VRIPPLE = 200mVP-P fIN = 1kHz INPUTS AC-COUPLED GND
MAX97000 toc18
IN-BAND OUTPUT SPECTRUM
MAX97000 toc19
IN-BAND OUTPUT SPECTRUM
FFM fIN = 1kHz
MAX97000 toc20
0 -20 -40 -60 -80 -100 2.5 3.0 3.5 4.0 4.5 5.0
0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120
0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120
SSM fIN = 1kHz
PSRR (dB)
5.5
0
5
10 FREQUENCY (kHz)
15
20
0
5
10 FREQUENCY (kHz)
15
20
SUPPLY VOLTAGE (V)
12
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
WIDEBAND OUTPUT SPECTRUM
MAX97000 toc21
MAX97000
WIDEBAND OUTPUT SPECTRUM
-10 OUTPUT AMPLITUDE (dBV) -20 -30 -40 -50 -60 -70 -80 -90 -100
-20 OUTPUT AMPLITUDE (dBV) -40 -60 -80 -100 -120 0.1 1 10
RBW = 100Hz FFM
RBW = 100Hz SSM
100
1000
0.1
1
10 FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
SPEAKER VOLUME GAIN vs. SPKVOL CODE
20 SPEAKER VOLUME GAIN (dB) 10 0 -10 -20 -30 -40 0 10 20 30 40 50 60 70
MAX97000 toc23
HARDWARE SHUTDOWN RESPONSE
MAX97000 toc24
30
1ms/div
SPKVOL CODE (NUMERIC)
SOFTWARE SHUTDOWN RESPONSE
MAX97000 toc25
SOFTWARE TURN-ON RESPONSE
MAX97000 toc26
SDA 2V/div
MAX97000 toc22
0
0
SHDN 2V/div
SPKR OUTPUT 500mV/div
SDA 2V/div
SPKR OUTPUT 1V/div
SPKR OUTPUT 1V/div
400s/div
4ms/div
13
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
HEADPHONE AMPLIFIER
THD+N vs. FREQUENCY
MAX97000 toc27
THD+N vs. FREQUENCY
MAX97000 toc28
THD+N vs. OUTPUT POWER
RLOAD = 32I
MAX97000 toc29
10
10
10
RLOAD = 32I
1 THD+N (%)
RLOAD = 16I
1 THD+N (%)
1 THD+N (%)
0.1
POUT = 25mW
0.1
POUT = 30mW
0.1
fIN = 1kHz
fIN = 6kHz
0.01
0.01
POUT = 5mW
0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100 0.001 0.01 0.1 1
POUT = 10mW
0.01
fIN = 100Hz
0.001 10 100 0 10 20 30 40 50 60 FREQUENCY (kHz) OUTPUT POWER (mW)
THD+N vs. OUTPUT POWER
MAX97000 toc30
POWER DISSIPATION vs. OUTPUT POWER
MAX97000 toc31
OUTPUT POWER vs. LOAD RESISTANCE
fIN = 1kHz THD+N = 10% 70 OUTPUT POWER (mW) 60 50 40 30 20 10 THD+N = 1%
MAX97000 toc32
10
RLOAD = 16I
180 160 POWER DISSIPATION (mW) 140 120 100 80 60 40 20
fIN = 1kHz POUT = PHPL + PHPR
80
1 THD+N (%)
fIN = 1kHz
0.1
RLOAD = 16I
fIN = 6kHz
RLOAD = 32I
0.01
fIN = 100Hz
0.001 0 10 20 30 40 50 60 70 80 OUTPUT POWER (mW)
0 0 10 20 30 40 50 60 70 80 90 OUTPUT POWER (mW)
0 1 10 100 1000 LOAD RESISTANCE (I)
OUTPUT POWER vs. LOAD RESISTANCE
60 OUTPUT POWER (mW) 50 40 30 20 10 0 1 10 100 1000 LOAD RESISTANCE (I) CCHARGE_PUMP = 0.47F fIN = 1kHz THD+N = 1% CCHARGE_PUMP = 2.2F CCHARGE_PUMP = 1F
MAX97000 toc33
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
VRIPPLE = 200mVP-P INPUTS AC-COUPLED GND
MAX97000 toc34
OUTPUT SPECTRUM
-20 -40 AMPLITUDE (dBV) -60 -80 -100 -120 -140 RLOAD = 32I fIN = 1kHz
MAX97000 toc35
70
0 -20 -40 -60 -80 -100 0.01 0.1 1 10 FREQUENCY (kHz)
0
PSRR (dB)
-160
100
0
4
8
12
16
20
24
FREQUENCY (kHz)
14
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
OUTPUT SPECTRUM
MAX97000 toc36
MAX97000
CROSSTALK vs. FREQUENCY
MAX97000 toc37
COMMON-MODE REJECTION RATIO vs. FREQUENCY
RLOAD = 16I -10 -20 CMRR (dB) -30 -40 -50 PREGAIN = 0dB -60 0.01 0.1 1 FREQUENCY (kHz) 10 100 PREGAIN = +9dB
MAX97000 toc38
0 -20 -40 AMPLITUDE (dBV) -60 -80 -100 -120 -140 -160 0 4 8 12 16 20 RLOAD = 16I fIN = 1kHz
0 RLOAD = 32I -20 CROSSTALK (dB) -40 -60 -80 -100 -120 HPL TO HPR HPR TO HPL
0
PREGAIN = +18dB
24
0.01
0.1
1 FREQUENCY (kHz)
10
100
FREQUENCY (kHz)
HEADPHONE VOLUME GAIN vs. HP_VOL CODE
0 -10 -20 -30 -40 -50 -60 -70 0 5 10 15 20 25 HP_VOL CODE (NUMERIC) 30 35
RIGHT AND LEFT
MAX97000 toc39
HARDWARE SHUTDOWN RESPONSE
MAX97000 toc40
10 HEADPHONE VOLUME GAIN (dB)
SHDN 2V/div
HPL/HPR 500mV/div
1ms/div
SOFTWARE SHUTDOWN RESPONSE
MAX97000 toc41
SOFTWARE TURN-ON RESPONSE
MAX97000 toc42
SDA 2V/div
SDA 2V/div
HPL/HPR 500mV/div
HPL/HPR 500mV/div
1ms/div
4ms/div
15
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
Typical Operating Characteristics (continued
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.)
ANALOG SWITCH
CLASS H OPERATION
MAX97000 toc43
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER
RLOAD = 32I EXTERNAL CLASS AB CONNECTED DIRECTLY TO COM1 AND COMR
MAX97000 toc44
HPVDD 1V/div HPVDD 0V HPL/HPR 200mV/div HPVSS 0V HPVSS 1V/div 10ms/div THD+N (%)
10
1
0.1 f = 100kHz 0.01
f = 6kHz
f = 100kHz 0.001 0 5 10 15 20 25 30 OUTPUT POWER (mW)
ON-RESISTANCE vs. VCOM
INC = 20mA VPVDD = 2.7V
MAX97000 toc45
BYPASS SWITCH OFF-ISOLATION
-20 OFF ISOLATION (dB) -40 -60 -80 -100 -120 -140
MAX97000 toc46
3.0 2.5 2.0 RON (I) 1.5 1.0 0.5 0 0
0
VPVDD = 3.7V VPVDD = 5.0V
VPVDD = 3.0V
1
2
3 VCOM (V)
4
5
6
0.01
0.1
1 FREQUENCY (kHz)
10
100
16
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Pin Configuration
TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5
MAX97000
+ MAX97000
A C1P C1N HPVDD HPVSS HPR
B
VDD
LDOIN
SDA
SCL
HPL
C
PVDD
PGND
GND
SHDN
BIAS
D
OUTN
COM1
COM2
INB1
INB2
E
OUTP
NC1
NC2
INA1
INA2
2.0mm x 2.0mm
Pin Description
BUMP A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 NAME C1P C1N HPVDD HPVSS HPR VDD LDOIN SDA SCL HPL PVDD PGND GND SHDN BIAS FUNCTION Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF capacitor between C1P and C1N. Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF capacitor between C1P and C1N. Headphone Amplifier Positive Power Supply. Bypass with a 1FF capacitor to PGND. Headphone Amplifier Negative Power Supply. Bypass with a 1FF capacitor to PGND. Headphone Amplifier Right Output LDO Output and Headphone Amplifier Supply. Bypass with a 1FF and a 10FF capacitor to GND. Do not externally supply. LDO Input. Generates VDD. Bypass with a 1FF capacitor to GND. Serial Data Input/Output. Connect a pullup resistor from SDA to the I2C bus supply. Serial-Clock Input. Connect a pullup resistor from SCL to the I2C bus supply. Headphone Amplifier Left Output Class D Power Supply. Bypass with a 1FF and a 10FF capacitor to PGND. Class D Power Ground and Charge Pump Ground Analog Ground. Active-Low Shutdown Common-Mode Bias. Bypass to GND with a 1FF capacitor.
17
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
Pin Description (continued)
BUMP D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 NAME OUTN COM1 COM2 INB1 INB2 OUTP NC1 NC2 INA1 INA2 Negative Speaker Output Analog Switch 1 Input Analog Switch 2 Input Input B1. Left or negative input. Input B2. Right or positive input. Positive Speaker Output Analog Switch 1 Output Analog Switch 2 Output Input A1. Left or negative input. Input A2. Right or positive input. FUNCTION
Detailed Description
The MAX97000 audio subsystem combines a mono speaker amplifier with a stereo headphone amplifier and an analog DPST switch. The high-efficiency 725mW Class D speaker amplifier operates directly from the battery and consumes no more than 1FA when in shutdown mode. The headphone amplifier utilizes a dual-mode charge pump and a Class H output stage to maximize efficiency while outputting a ground-referenced signal that does not require output coupling capacitors. The headphone and speaker amplifiers have independent volume control and on/off control. The four inputs are configurable as two differential inputs or four singleended inputs. All control is performed using the 2-wire, I2C interface. The speaker amplifier incorporates a distortion limiter to automatically reduce the volume level when excessive
clipping occurs. This allows high gain for low-level signals without compromising the quality of large signals. The MAX97000 includes an internal regulator (LDOIN) to generate VDD. The regulator allows single-supply operation directly from a Li+ battery.
Internal Linear Regulator
The MAX97000 signal path consists of flexible inputs, signal mixing, volume control, and output amplifiers (Figure 2). The inputs can be configured for singleended or differential signals (Figure 3). The internal preamplifiers feature programmable gain settings using internal resistors and an external gain setting using a trimmed internal feedback resistor. The external option allows any desired gain to be selected. Following preamplification, the input signals are mixed, volume adjusted, and routed to the headphone and speaker amplifiers based on the desired configuration.
Signal Path
INA2 INA1
INPUT A -6dB TO +18dB MIXER AND MUX
-64dB TO +6dB
0/3dB
INB2 INB1
-64dB TO +6dB
0/3dB
INPUT B -6dB TO +18dB -30dB TO +20dB +12dB
Figure 2. Signal Path 18
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
STEREO SINGLE-ENDED
IN_2 (R) R
TO MIXER
IN_1 (L) L
DIFFERENTIAL IN_2 (+)
IN_1 (-) TO MIXER
Figure 3. Differential and Stereo Single-Ended Input Configurations
The MAX97000 features independent mixers for the left headphone, right headphone, and speaker paths. Each output can select any combination of any inputs. This allows for mixing two audio signals together and routing independent signals to the headphone and speaker amplifiers. If one of the inputs is not selected by either mixer, it is automatically powered down to save power.
Mixers
The MAX97000 Class D speaker amplifier utilizes active emissions limiting and spread-spectrum modulation to minimize the EMI radiated by the amplifier.
Class D Speaker Amplifier
19
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
Ultra-Low EMI Filterless Output Stage Traditional Class D amplifiers require the use of external LC filters or shielding to meet EN55022B electromagnetic-interference (EMI) regulation standards. Maxim's patented active emissions limiting edge-rate control circuitry and spread-spectrum modulation reduces EMI emissions, while maintaining up to 87% efficiency. Maxim's patented spread-spectrum modulation mode flattens wideband spectral components, while proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency. The MAX97000's spread-spectrum modulator randomly varies the switching frequency by Q20kHz around the center frequency (250kHz). Above 10MHz, the wideband spectrum looks like noise for EMI purposes (see Figure 4).
40 30 AMPLITUDE (dBV/m) 20 10 0 -10 30 40 30 AMPLITUDE (dBV/m) 20 10 0 -10 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 FREQUENCY (MHz) 60 80 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (MHz)
Figure 4. EMI with 15cm of Speaker Cable
20
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Distortion Limiter The MAX97000 speaker amplifiers integrate a limiter to provide speaker protection and audio compression. When enabled, the limiter monitors the audio signal at the output of the Class D speaker amplifier and decreases the gain if the distortion exceeds the predefined threshold. The limiter automatically tracks the battery voltage to reduce the gain as the battery voltage drops. Figure 5 shows the typical output vs. input curves with and without the distortion limiter. The dotted line shows the maximum gain for a given distortion limit without the distortion limiter. The solid line shows how, with the distortion limiter enabled, the gain can be increased without exceeding the set distortion limit. When the limiter is enabled, selecting a high gain level results in peak signals being attenuated while low signals are left unchanged. This increases the perceived loudness without the harshness of a clipped waveform. The MAX97000 integrates a DPST analog audio switch. This switch can be used to disconnect an independent audio signal, or drive the 8I speaker by connecting NC1 and NC2 to OUTN and OUTP, respectively. Unlike discrete solutions, the switch design reduces coupling of Class D switching noise to the COM_ inputs. This eliminates the need for a costly T-switch. Drive COM1 and COM2 with a low-impedance source to minimize noise on the pins. In applications that do not require the analog switch, leave COM1, COM2, NC1, and NC2 unconnected.
Headphone Amplifier
DirectDrive Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier. Maxim's patented DirectDrive(R) architecture uses a charge pump to create an internal negative supply voltage. This allows the headphone outputs of the MAX97000 to be biased at GND while operating from a single supply (Figure 6). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220FF, typ) capacitors, the MAX97000 charge pump requires three small ceramic capacitors,
MAX97000
Analog Switch
VDD
VDD / 2
GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD
VOUT MAXIMUM THD+N LEVEL
SGND
VIN
-VDD DirectDrive AMPLIFIER BIASING SCHEME
Figure 5. Limiter Gain Curve
Figure 6. Traditional Amplifier Output vs. MAX97000 DirectDrive Output
DirectDrive is a registered trademark of Maxim Integrated Products, Inc. 21
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
conserving board space, reducing cost, and improving the frequency response of the headphone amplifier. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics for details of the possible capacitor sizes. There is a low DC voltage on the amplifier outputs due to amplifier offset. However, the offset of the MAX97000 is typically Q0.15mV, which, when combined with a 32I load, results in less than 5FA of DC current flow to the headphones. In addition to the cost and size disadvantages of the DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier's low-frequency response and can distort the audio signal. Previous attempts at eliminating the output-coupling capacitors involved biasing the headphone return (sleeve) to the DC bias voltage of the headphone amplifiers. This method raises some issues: * The sleeve is typically grounded to the chassis. Using the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design. During an ESD strike, the amplifier's ESD structures are the only path to system ground. Thus, the amplifier must be able to withstand the full energy from an ESD strike. When using the headphone jack as a line out to other equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers. To prevent audible gliches when transitioning from the Q(VDD/2) output mode to the QVDD output mode, the charge pump transitions very quickly. This quick change draws significant current from VDD for the duration of the transition. The bypass capacitor on VDD supplies the required current and prevents droop on VDD. The charge pump's dynamic switching mode can be turned off through the I2C interface. The charge pump can then be forced to output either Q(VDD/2) or QVDD regardless of input signal level. Class H Operation A Class H amplifier uses a Class AB output stage with power supplies that are modulated by the output signal. In the case of the MAX97000, two nominal power-supply differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V) are available from the charge pump. Figure 7 shows the operation of the output-voltage-dependent power supply. Low-Power Mode To minimize power consumption when using the headphone amplifier, enable the low-power mode. In this mode, the headphone mixers and volume control are bypassed and shut down. The MAX97000 uses a slave address of 0x9A or 1001101RW. The address is defined as the 7 most significant bits (MSBs) followed by the read/write bit. Set the read/write bit to 1 to configure the MAX97000 to read mode. Set the read/write bit to 0 to configure the MAX97000 to write mode. The address is the first byte of information sent to the MAX97000 after the START (S) condition.
*
I2C Slave Address
*
Charge Pump The MAX97000's dual-mode charge pump generates both the positive and negative power supply for the headphone amplifier. To maximize efficiency, both the charge pump's switching frequency and output voltage change based on signal level. When the input signal level is less than 10% of VDD, the switching frequency is reduced to a low rate. This minimizes switching losses in the charge pump. When the input signal exceeds 10% of VDD, the switching frequency increases to support the load current. For input signals below 25% of VDD, the charge pump generates Q(VDD/2) to minimize the voltage drop across the amplifier's power stage and thus improve efficiency. Input signals that exceed 25% of VDD cause the charge pump to output QVDD. The higher output voltage allows for full output power from the headphone amplifier.
1.8V 0.9V VTH_H OUTPUT VOLTAGE VTH_L -0.9V -1.8V HPVDD 32ms
HPVSS
32ms
Figure 7. Class H Operation 22
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Nine internal registers program the MAX97000. Table 1 lists all the registers, their addresses, and power-onreset states. Register 0xFF indicates the device revision.
I2C Registers
Write zeros to all unused bits in the register table when updating the register, unless otherwise noted. Tables 2 through 7 describe each bit.
MAX97000
Table 1. Register Map
REGISTER STATUS Input Gain Headphone Mixers Speaker Mixer Headphone Left Headphone Right Speaker Reserved Limiter Power Management Charge Pump REVISION ID Rev ID REV 0xFF 0x00 R SHDN 0 0 ZCD LPGAIN FFM 0 INADIFF INBDIFF HPLMIX 0 SLEW 0 SPKM 0 THDCLP LPMODE 0 0 SPKEN 0 0 0 0 0 0 0 0 HPLM HPRM 0 PGAINA PGAINB HPRMIX SPKMIX HPLVOL HPRVOL SPKVOL 0 0 HPLEN 0 0 0 HPREN CPSEL 0 THDT1 SWEN FIXED 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W
Table 2. Input Register
REGISTER BIT 7 NAME INADIFF DESCRIPTION Input A Differential Mode. Configures the input A channel as either a mono differential signal (INA = INA2 - INA1) or as a stereo signal (INA1 = left, INA2 = right). 0 = Stereo single-ended 1 = Differential Input B Differential Mode. Configures the input B channel as either a mono differential signal (INB = INB2 - INB1) or as a stereo signal (INB1 = left, INB2 = right). 0 = Stereo single-ended 1 = Differential Input A Preamp Gain. Set the input gain to maximize output signal level for a given input signal range to improve the SNR of the system. PGAINA = 111 switches to a trimmed 20kI feedback resistor for external gain setting. VALUE 000 001 010 011 100 101 110 111 LEVEL (dB) -6 -3 0 3 6 9 18 External 23
6
INBDIFF
0x00
5
4
PGAINA
3
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
Table 2. Input Register (continued)
REGISTER BIT 2 NAME DESCRIPTION Input B Preamp Gain. Set the input gain to maximize output signal level for a given input signal range to improve the SNR of the system. PGAINB = 111 switches to a trimmed 20kI feedback resistor for external gain setting. VALUE LEVEL (dB) 000 -6 001 -3 010 0 011 3 100 6 101 9 110 18 111 External
1
PGAINB
0
Mixers
Table 3. Mixer Registers
REGISTER BIT 7 6 HPLMIX 5 4 0x01 3 2 HPRMIX 1 0 3 2 0x02 1 0 SPKMIX NAME DESCRIPTION Left Headphone Mixer. Selects which of the four inputs is routed to the left headphone output. VALUE 0000 xxx1 xx1x x1xx 1xxx INPUT No input INA1 (Disabled when INADIFF = 1) INA2 (Select when INADIFF = 1) INB1 (Disabled when INBDIFF = 1) INB2 (Select when INBDIFF = 1)
Right Headphone Mixer. Selects which of the four inputs is routed to the right headphone output. VALUE 0000 xxx1 xx1x x1xx 1xxx INPUT No input INA1 (Disabled when INADIFF = 1) INA2 (Select when INADIFF = 1) INB1 (Disabled when INBDIFF = 1) INB2 (Select when INBDIFF = 1)
Speaker Mixer. Selects which of the four inputs is routed to the speaker output. VALUE 0000 xxx1 xx1x x1xx 1xxx INPUT No input INA1 (Disabled when INADIFF = 1) INA2 (Select when INADIFF = 1) INB1 (Disabled when INBDIFF = 1) INB2 (Select when INBDIFF = 1)
24
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Volume Control
MAX97000
Table 4. Volume Control Registers
REGISTER BIT NAME DESCRIPTION Zero-Crossing Detection. Determines whether zero-crossing detection is used on all volume control changes to reduce clicks and pops. Disabling zero-crossing detection allows volume changes to occur immediately. 0 = Enabled 1 = Disabled Volume Slewing. Determines whether volume slewing is used on all volume control changes to reduce clicks and pops. When enabled, volume changes cause the MAX97000 to ramp through intermediate volume settings whenever a change to the volume is made. If ZCD = 1, slewing occurs at a rate of 0.2ms per step. If ZCD = 0, slew time depends on the input signal. Write a 1 to this bit to disable slewing and implement volume changes immediately. This bit also activates soft-start at power-on and soft-stop and power-off. 0 = Enabled 1 = Disabled Left Headphone Mute 0 = Unmuted 1 = Muted Left Headphone Volume VALUE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F LEVEL (dB) -64 -60 -56 -52 -48 -44 -40 -37 -34 -31 -28 -25 -22 -19 -16 -14 VALUE 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F LEVEL (dB) -12 -10 -8 -6 -4 -2 -1 0 1 2 3 4 4.5 5 5.5 6
7
ZCD
6
SLEW
5 0x03
HPLM
4
3
2 HPLVOL
1
0
25
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
Table 4. Volume Control Registers (continued)
REGISTER BIT 7 NAME LPGAIN DESCRIPTION Low-Power Mode Gain. Controls the headphone amplifier gain when LPMODE 0. 0 = 0dB 1 = 3dB Right Headphone Mute 0 = Unmuted 1 = Muted Right Headphone Volume VALUE LEVEL (dB) VALUE LEVEL (dB) 0x00 -64 0x10 -12 0x01 -60 0x11 -10 0x02 -56 0x12 -8 0x03 -52 0x13 -6 0x04 -48 0x14 -4 0x05 -44 0x15 -2 0x06 -40 0x16 -1 0x07 -37 0x17 0 0x08 -34 0x18 1 0x09 -31 0x19 2 0x0A -28 0x1A 3 0x0B -25 0x1B 4 0x0C -22 0x1C 4.5 0x0D -19 0x1D 5 0x0E -16 0x1E 5.5 0x0F -14 0x1F 6 Fixed-Frequency Oscillation. Removes spread spectrum from the class D oscillator. 0 = Spread-spectrum mode 1 = Fixed-frequency mode Speaker Mute 0 = Unmuted 1 = Mute Speaker Volume VALUE 0x00-0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 LEVEL (dB) -30 -26 -22 -18 -14 -12 -10 -8 -6 -4 -2 0 1 2 VALUE 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 LEVEL (dB) 3 4 5 6 7 8 9 10 11 12 12.5 13 13.5 14 VALUE 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F LEVEL (dB) 14.5 15 15.5 16 16.5 17 17.5 18 18.5 19 19.5 20
5 4
HPRM
3 0x04 2 HPRVOL
1
0
7
FFM
6
SPKM
5 4 0x05 3 SPKVOL 2
1
0
26
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Table 5. Distortion Limiter Register
REGISTER BIT 7 NAME Distortion Limit VALUE 0000 0001-1001 1010 1011 1100 1101 1110 1111 THD LIMIT (%) Disabled P4 P5 P6 P8 P 11 P 12 P 15 DESCRIPTION
Distortion Limiter
MAX97000
6 THDCLP 0x07 5
4
0
THDT1
Distortion Release Time Constant 0 = 1.4s 1 = 2.8s
Table 6. Power Management Register
REGISTER BIT 7 NAME SHDN Software Shutdown 0 = Device disabled 1 = Device enabled DESCRIPTION
Power Management
6 LPMODE 5
Low-Power Headphone Mode. Enables low-power headphone mode. When activated this mode directly connects the selected channel to the headphone amplifiers, bypassing the mixers and the volume control. Additionally, low-power mode disables the speaker path. VALUE 00 01 10 11 INPUT Disabled INA (SE) Connected to the headphone output INB (SE) Connected to the headphone output INA (Diff) to HPL and INB (Diff) to HPR
0x08 4 SPKEN
Speaker Amplifier Enable 0 = Disabled 1 = Enabled Left Headphone Amplifier Enable 0 = Disabled 1 = Enabled Right Headphone Amplifier Enable 0 = Disabled 1 = Enabled Analog Switch 0 = Open 1 = Closed
2
HPLEN
1
HPREN
0
SWEN
27
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
Table 7. Charge-Pump Control Register
REGISTER BIT 1 0x09 0 FIXED NAME CPSEL DESCRIPTION Charge-Pump Output Select. Works with the FIXED to set Q1.8V or Q0.9V outputs on HPVDD and HPVSS. Ignored when FIXED = 0. 0 = Q1.8V on HPVDD/HPVSS 1 = Q0.9V on HPVDD/HPVSS Class H Mode. When enabled, this bit forces the charge pump to generate static power rails for HPVDD and HPVSS, instead of dynamically adjusting them based on output signal level. 0 = Class H mode 1 = Fixed-supply mode
Charge-Pump Control
The MAX97000 features an I2C/SMBusK-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX97000 and the master at clock rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the MAX97000 by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX97000 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX97000 transmits the proper slave address followed by a series of nine SCL pulses. The MAX97000 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500I, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500I, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX97000 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section).
28
I2C Serial Interface
S SCL
Sr
P
SDA
Figure 8. START, STOP, and REPEATED START Conditions
START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 8). A START condition from the master signals the beginning of a transmission to the MAX97000. The master terminates transmission and frees the bus by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The MAX97000 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the MAX97000 the seven most significant bits are 1001101. Setting the read/write bit to 1 (slave address = 0x9B) configures the MAX97000 for read mode. Setting the read/write bit to 0 (slave address = 0x9A) configures the MAX97000 for write mode. The address is the first byte of information sent to the MAX97000 after the START condition.
SMBus is a trademark of Intel Corp.
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX97000 uses to handshake receipt each byte of data when in write mode (Figure 9). The MAX97000 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master will retry communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX97000 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not-acknowledge is sent when the master reads the final byte of data from the MAX97000, followed by a STOP condition. Write Data Format A write to the MAX97000 includes transmission of a START condition, the slave address with the R//W bit set to 0, 1 byte of data to configure the internal register address pointer, 1 or more bytes of data, and a STOP condition. Figure 10 illustrates the proper frame format for writing 1 byte of data to the MAX97000. Figure 11 illustrates the frame format for writing n-bytes of data to the MAX97000.
CLOCK PULSE FOR ACKNOWLEDGMENT
MAX97000
START CONDITION SCL 1 28
9 NOT ACKNOWLEDGE
SDA ACKNOWLEDGE
Figure 9. Acknowledge
ACKNOWLEDGE FROM MAX97000 B7 ACKNOWLEDGE FROM MAX97000 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX97000 REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0
Figure 10. Writing 1 Byte of Data to the MAX97000
ACKNOWLEDGE FROM MAX97000 ACKNOWLEDGE FROM MAX97000 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX97000 REGISTER ADDRESS A B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE 1 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A ACKNOWLEDGE FROM MAX97000 B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE n 1 BYTE A P
Figure 11. Writing n-Bytes of Data to the MAX97000 29
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX97000. The MAX97000 acknowledges receipt of the address byte during the master-generated 9th SCL pulse. The second byte transmitted from the master configures the MAX97000's internal register address pointer. The pointer tells the MAX97000 where to write the next byte of data. An acknowledge pulse is sent by the MAX97000 upon receipt of the address pointer data. The third byte sent to the MAX97000 contains the data that is written to the chosen register. An acknowledge pulse from the MAX97000 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0x09 are reserved. Do not write to these addresses. Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX97000 acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. The first byte transmitted from the MAX97000 are the contents of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from register 0x00. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX97000's slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX97000 then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 12 illustrates the frame format for reading 1 byte from the MAX97000. Figure 13 illustrates the frame format for reading multiple bytes from the MAX97000.
ACKNOWLEDGE FROM MAX97000 S SLAVE ADDRESS R/W 0
ACKNOWLEDGE FROM MAX97000 REGISTER ADDRESS A
ACKNOWLEDGE FROM MAX97000 Sr SLAVE ADDRESS R/W 1
NOT ACKNOWLEDGE FROM MASTER
A
DATA BYTE 1 BYTE
A
P
REPEATED START
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 12. Reading 1 Byte of Data from the MAX97000
ACKNOWLEDGE FROM MAX97000 S SLAVE ADDRESS R/W 0
ACKNOWLEDGE FROM MAX97000 REGISTER ADDRESS A
ACKNOWLEDGE FROM MAX97000 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 13. Reading n-Bytes of Data from the MAX97000
30
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Applications Information
Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier's output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The traditional PWM scheme uses large differential output swings (2 x VDD peak-to-peak) and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency. The MAX97000 does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution. Because the frequency of the MAX97000 output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power can be damaged. For optimum results, use a speaker with a series inductance > 10FH. Typical 8I speakers exhibit series inductances in the 20FH to 100FH range. GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz and its harmonics that is easily demodulated by audio amplifiers. The MAX97000 is designed specifically to reject RF signals; however, PCB layout has a large impact on the susceptibility of the end product.
Filterless Class D Operation
Additional RF immunity can also be obtained from relying on the self-resonant frequency of capacitors as it exhibits the frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self-resonance at RF frequencies. These capacitors when placed at the input pins can effectively shunt the RF noise at the inputs of the MAX97000. For these capacitors to be effective, they must have a low-impedance, low-inductance path to the ground plane. Do not use microvias to connect to the ground plane as these vias do not conduct well at RF frequencies.
MAX97000
Component Selection
Optional Ferrite Bead Filter Additional EMI suppression can be achieved using a filter constructed from a ferrite bead and a capacitor to ground (Figure 14). Use a ferrite bead with low DC resistance, high-frequency (> 600MHz) impedance between 100I and 600I, and rated for at least 1A. The capacitor value varies based on the ferrite bead chosen and the actual speaker lead length. Select a capacitor less than 1nF based on EMI performance. Input Capacitor An input capacitor, CIN, in conjunction with the input impedance of the MAX97000 line inputs forms a highpass filter that removes the DC bias from an incoming analog signal. The AC-coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the highpass filter is given by:
RF Susceptibility
f-3dB =
1 2RINCIN
In RF applications, improvements to both layout and component selection decrease the MAX97000's susceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths should be kept below 1/4 of the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the MAX97000. The wavelength (l) in meters is given by: l = c/f where c = 3 x 108 m/s, and f = the RF frequency of interest. Route audio signals on middle layers of the PCB to allow ground planes above and below shield them from RF interference. Ideally the top and bottom layers of the PCB should primarily be ground planes to create effective shielding.
Choose CIN such that f-3dB is well below the lowest frequency of interest. For best audio quality, use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with highvoltage coefficients, such as ceramics, may result in increased distortion at low frequencies.
OUTP
MAX97000
OUTN
Figure 14. Optional Class D Ferrite Bead Filter 31
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000
Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100mI for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric. Charge-Pump Flying Capacitor The value of the flying capacitor (connected between C1N and C1P) affects the output resistance of the charge pump. A value that is too small degrades the device's ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of the flying capacitor reduces the charge-pump output resistance to an extent. Above 1FF, the on-resistance of the internal switches and the ESR of external chargepump capacitors dominate. Charge-Pump Holding Capacitor The holding capacitor (bypassing HPVDD and HPVSS) value and ESR directly affect the ripple on the supply. Increasing the capacitor's value reduces output ripple. Likewise, decreasing the ESR reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics section for more information. Supply Bypassing, Layout, and Grounding Proper layout and grounding are essential for optimum performance. Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas. Connect GND and PGND directly to the ground plane using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the analog audio signals. Place the capacitor between C1P and C1N as close as possible to the MAX97000 to minimize trace length from C1P to C1N. Inductance and resistance added between C1P and C1N reduce the output power of the headphone amplifier. Bypass HPVDD and HPVSS with capacitors located close to the pins with a short trace length to PGND. Close decoupling of HPVDD and HPVSS minimizes supply ripple and maximizes output power from the headphone amplifier. Bypass PVDD to PGND with as little trace length as possible. Connect OUTP and OUTN to the speaker using the shortest and widest traces possible. Reducing trace length minimizes radiated EMI. Route OUTP/OUTN as a differential pair on the PCB to minimize the loop area and thereby the inductance of the circuit. If filter components are used on the speaker outputs, be sure to locate them as close to the MAX97000 as possible to ensure maximum effectiveness. Minimize the trace length from any ground tied passive components to PGND to further minimize radiated EMI. An evaluation kit (EV kit) is available to provide an example layout for the MAX97000. The EV kit allows quick setup of the MAX97000 and includes easy-to-use software allowing all internal registers to be controlled. WLP Applications Information For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note: UCSP - A Wafer-Level Chip-Scale Package on Maxim's website at www.maxim-ic.com/ucsp. See Figure 15 for the recommended PCB footprint for the MAX97000.
0.24mm
0.21mm
Figure 15. Recommended PCB Footprint
32
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 25WLP PACKAGE CODE W252F2+1 DOCUMENT NO. 21-0453
MAX97000
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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(c)
33
2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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